Relatively small (e.g., 3 to 5 IRE) signals encoding digital information can be admixed together with composite video signals without being readily evident in television pictures generated from those composite video signals if suitable restrictions on the digital signal format are observed. Jian Yang describes a system for doing this in his U.S. patent application Ser. No. 08/141,070 filed Nov. 26, 1993, entitled "APPARATUS FOR PROCESSING NTSC TV SIGNALS HAVING DIGITAL SIGNALS ON QUADRATURE-PHASE VIDEO CARRIER", and incorporated by reference herein. The inventions described in U.S. patent application Ser. No. 08/141,070, like the inventions described herein, are assigned to Samsung Electronics Co., Ltd., pursuant to pre-existing employee agreement so to assign inventions made within the scope of employment. U.S. patent application Ser. No. 08/141,070 describes binary phase-shift-keyed (BPSK) modulation of a suppressed carrier that is the same frequency as a video carrier and is in quadrature phasing therewith. U.S. patent application Ser. No. 08/141,070 advocates the BPSK signals being constrained to about 2 MHz bandwidth so as to avoid crosstalk into chroma in TV receivers that separate chroma from luma without recourse to comb filtering. U.S. patent application Ser. No. 08/141,070 indicates a preference for passing the data to be transmitted through a partial-response filter for processing the data so that it can be recovered by multi-level symbol decision circuitry after line-comb filtering in the digital signal receiver to separate PSK subcarrier from the luminance portion of the composite video signal. U.S. patent application Ser. No. 08/141,070 also advocates repeating frames of the BPSK in antiphase in successive pairs of consecutive frames of the NTSC television signal. Such repetition of data in pairs of frames makes the BPSK accompanying the composite video signal detected from the NTSC television signal less apparent in images that are generated from the composite video signal for viewing on a screen. Such repetition of data in pairs of frames also provides a basis for using frame-comb filtering in the digital signal receiver to separate the BPSK from the luminance portion of the composite video signal that describes static portions of successive television images.
U.S. patent application Ser. No. 08/141,070 describes the problems encountered in the digital signal receiver when the BPSK is to be digitized after its detection, assuming that the flash converter normally used for digitizing composite video signals is used. The remnants of composite video signal above 750 kHz, which accompany the BPSK when the BPSK is synchronously detected, can be expected to be relatively large compared to the BPSK at times. These large composite video signal remnants take up much of the dynamic range the flash converter provides for analog input signal, if digitization is done just after synchronous detection of the BPSK, and the relatively small BPSK signal tends to be inadequately resolved owing to the quantizing noise of a flash converter that has only eight bits resolution or so. While flash converters that have as many as twelve bits can be constructed, they are too expensive to be used in electronic products for the mass market. U.S. patent application Ser. No. 08/141,070 advocates the use of analog line-comb filtering of the BPSK signals before their digitization, in order to reduce the relative size of the remnants of composite video signal above 750 kHz that accompany the BPSK. The BPSK signal can then be resolved in more of the digital output range of the flash converter to reduce symbol error.
While flash converters increase in price very rapidly with increase in their bit resolution, the increase in price is relatively modest for increased bandwidth beyond the 2 MHz constraint on BPSK bandwidth suggested in U.S. patent application Ser. No. 08/141,070. The 2 MHz constraint on BPSK bandwidth requires 4 MHz sampling rate in order that maximum symbol rate be adequately sampled, and 8-bit flash converters operable at sixteen, thirty-two or even sixty-four times this sample rate are relatively modest in price. It is pointed out in U.S. patent application Ser. No. 08/141,071 that oversampling conversion methods can be used to secure increased effective bit resolution from such 8-bit flash converters. Oversampling at sixteen times the 4 MHz sample rate can secure as much as twelve bits effective resolution, to digitize the detected BPSK without its being lost in the quantizing noise, even though the detected BPSK is relatively small compared to the accompanying composite video signal which occupies most of the dynamic range of the flash converter.
A type of oversampling converter known as a "sigma-delta" analog-to-digital converter is familiar to circuit designers for obtaining multiple-bit resolution from a basic single-bit-resolution ADC. Sigma-delta analog-to-digital converters for increasing the bit resolution of a basic multiple-bit-resolution analog-to-digital converter, though not commonplace, are known. In their operation, sigma-delta analog-to-digital converters feed back digital output signal to a digital-to-analog converter and thence to an analog subtractor, for generating an error signal to be digitized by the basic ADC in subsequent steps of the oversampling procedure. While the quantization noise arising during analog-to-digital conversion is suppressed by the degenerative feedback, being shifted upward in frequency so it can be suppressed by lowpass digital filtering, the quantization noise arising during digital-to-analog conversion is not. For this reason, single-bit coders, which avoid the problem of DAC error, have been preferred in sigma-delta analog-to-digital converters. ADCs using single-bit coders are not suitable for the digital signal receivers receiving BPSK at over 1 megabit/second rate, because the oversampling that must be done in order to meet bit-resolution requirements requires sampling rates too high to be practical. The problems encountered when attempting to use commonly known sigma-delta ADCs using multiple-bit coders led Bolger to pursue oversampling methods other than those using sigma-delta modulation, as described in his U.S. patent application Ser. No. 08/141,071.
T. C. Leslie and B. Singh of Plessey Research Caswell Ltd. in their paper "An Improved Sigma-Delta Modulator Architecture", 1990 IEEE SYMPOSIUM ON CIRCUITS & SYSTEMS, 90 CH 2868-8900000-0372, pp. 372-375, incorporated herein by reference, describe increasing the bit resolution of a basic multiple-bit-resolution ADC by using a sigma-delta procedure in which only a single bit of the basic multiple-bit-resolution ADC output signal is converted back to analog signal for feedback purposes during each oversampling step. The inventors have discerned that the Leslie and Singh type of sigma-delta architecture is well-suited to solving the problems of analog-to-digital conversion encountered after detecting relatively low-power BPSK buried in NTSC television signals.